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1. general description the pcal6416a is a 16-bit general purpose i/o expander that provides remote i/o expansion for most microcon troller families via the i 2 c-bus interface. nxp i/o expanders provide a simple solution when additional i/os are needed while keeping interconnections to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, push bu ttons, keypad, etc. in addition to providing a flexible set of gpios, it simplifies interco nnection of a processor running at one voltage level to i/o devices operating at a different (usually higher) voltage level. the pcal6416a has built-in level shifting feature that make s these devices extremely flexible in mixed signal environments where communication between incompatible i/o voltages is required. its wide v dd range of 1.65 v to 5.5 v on the dual power rail allows seamless communications with next-generation low voltage microprocessors and microcontrollers on the interface side (sda/scl) and peripherals at a higher voltage on the port side. there are two supply voltages for pcal6416a: v dd(i2c-bus) and v dd(p) . v dd(i2c-bus) provides the supply voltage for the interfac e at the master side (for example, a microcontroller) and the v dd(p) provides the supply for core circuits and port p. the bidirectional voltage level translation in the pcal6416a is provided through v dd(i2c-bus) . v dd(i2c-bus) should be connected to the v dd of the external scl/sda lines. this indicates the v dd level of the i 2 c-bus to the pcal6416a, while the voltage level on port p of the pcal6416a is determined by the v dd(p) . the pcal6416a contains the pca6416a register set of four pairs of 8-bit configuration, input, output, and polarity inversion registers and additionally, the pcal6416a has agile i/o, which are additional features specif ically designed to enhance the i/o. these additional features are: programmable output drive st rength, latchable inputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register, programmable open-drain or push-pull outputs. the pcal6416a is a pin-to-pin replacement to the pca6416a, however, the pc al6416a powers up with all i/o interrupts masked. this mask default allows for a boar d bring-up free of spurious interrupts at power-up. at power-on, the i/os are configured as inputs. however, the system master can enable the i/os as either inputs or outputs by writing to the i/o configuration bits. the data for each input or output is kept in the corresp onding input or output re gister. the polarity of the input port register can be inverted with the polarity inversion register, saving external logic gates. programmable pull-up and pull-down resistors eliminate the need for discrete components. pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander with interrupt output, reset, an d configuration registers rev. 3 ? 24 december 2012 product data sheet
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 2 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander the system master can reset the pcal6416a in the event of a time-out or other improper operation by asserti ng a low in the reset input. the power-on reset puts the registers in their default state and initializes the i 2 c-bus/smbus state machine. the reset pin causes the same reset/in itialization to occur witho ut depowering the part. the pcal6416a open-drain interrupt (int ) output is activated when any input state differs from its corresponding input port register st ate and is used to indicate to the system master that an input state has changed. int can be connected to the interrupt input of a microcontroller. by sending an interrupt signal on this line, the remote i/o can inform the microcontroller if there is incoming data on its ports without having to communicate via the i 2 c-bus. thus, the pcal6416a can remain a simple slave device. the input latch feature holds or latches the input pin state and keeps the logic values that created the interrupt until the master can service the interrupt. this minimizes the host?s interrup t service response fo r fast moving inputs. the device port p outputs have 25 ma sink ca pabilities for directly driving leds while consuming low device current. one hardware pin (addr) can be used to program and vary the fixed i 2 c-bus address and allow up to two devices to share the same i 2 c-bus or smbus. 2. features and benefits ? i 2 c-bus to parallel port expander ? operating power supply voltage range of 1.65 v to 5.5 v ? allows bidirectional voltage-level tr anslation and gpio expansion between: ? 1.8v scl/sda and 1.8v, 2.5v, 3.3v or 5v portp ? 2.5v scl/sda and 1.8v, 2.5v, 3.3v or 5v portp ? 3.3v scl/sda and 1.8v, 2.5v, 3.3v or 5v portp ? 5v scl/sda and 1.8v, 2.5v, 3.3v or 5v portp ? low standby current consumption: ? 1.5 ? a typical at 5 v v dd ? 1.0 ? a typical at 3.3 v v dd ? schmitt trigger action allows slow input tr ansition and better swit ching noise immunity at the scl and sda inputs ? v hys = 0.18 v (typical) at 1.8 v ? v hys = 0.25 v (typical) at 2.5 v ? v hys = 0.33 v (typical) at 3.3 v ? v hys = 0.5 v (typical) at 5 v ? 5 v tolerant i/o ports ? active low reset input (reset ) ? open-drain active low interrupt output (int ) ? 400 khz fast-mode i 2 c-bus ? internal power-on reset ? power-up with all channels configured as inputs ? no glitch on power-up ? noise filter on scl/sda inputs
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 3 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander ? latched outputs with 25 ma drive maximu m capability for directly driving leds ? latch-up performance exceeds 100 ma per jesd 78, class ii ? esd protection exceeds jesd 22 ? 2000 v human-body model (a114-a) ? 1000 v charged-device model (c101) ? packages offered: tssop24, hvqfn24, vfbga24, xfbga24 2.1 agile i/o features ? software backward compatible with pca6416a with interrupts disabled at power-up ? pin-to-pin drop-in replacement with pca6416a ? output port configuration: bank select able push-pull or open-drain output stages ? interrupt status: read-only register identifies the source of an interrupt ? bit-wise i/o programming features: ? output drive strength: four programmable drive strengths to reduce rise and fall times in low-capacitance applications ? input latch: input port register values changes are kept until the input port register is read ? pull-up/pull-down enable: floating input or pull-up/pull-down resistor enable ? pull-up/pull-down selection: 100 k ? pull-up/pull-down resistor selection ? interrupt mask: mask prevents the generation of the interrupt when input changes state to prevent spurious interrupts 3. ordering information table 1. ordering information type number topside mark package name description version pcal6416aev l16a vfbga24 plastic very thin fine-pitch ball grid array package; 24 balls; body 3 ? 3 ? 0.85 mm sot1199-1 pcal6416aex l16 xfbga24 plastic, extremely thin fine-pitch ball grid array package; 24 balls; body 2 ? 2 ? 0.5 mm sot1342-1 pcal6416ahf l16a hwqfn24 plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 ? 4 ? 0.75 mm sot994-1 PCAL6416APW pcal6416a tssop24 pla stic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 4 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 3.1 ordering options 4. block diagram table 2. ordering options type number orderable part number package packing method minimum order quantity temperature range pcal6416aev pcal6416aevj vfbga24 reel pack, smd, 13-inch 6000 t amb = ? 40 ? c to +85 ?c pcal6416aex xfbga24 reel pack, smd, 7-inch t amb = ? 40 ? c to +85 ?c pcal6416ahf pcal6416ahf,128 hwqfn24 reel pack, smd, 13-inch, turned 6000 t amb = ? 40 ? c to +85 ?c PCAL6416APW PCAL6416APW,118 tssop24 reel pack, smd, 13-inch 2500 t amb = ? 40 ? c to +85 ?c all i/os are set to inputs at reset. fig 1. block diagram of pcal6416a (positive logic) 002aaf962 int i 2 c-bus control interrupt logic pcal6416a lp filter addr input filter shift register sda scl 16 bits write pulse read pulse power-on reset v dd(p) v ss i/o port p0_0 to p0_7 p1_0 to p1_7 reset v dd(i2c-bus) i/o control
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 5 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 5. pinning information 5.1 pinning the exposed center pad, if used, must be connected only as a secondary ground or must be left electrically open. fig 2. pin configuration for tssop24 fig 3. pin configuration for hwqfn24 an empty cell indicates no ball is populated at that grid point. fig 4. pin configuration for vfbga24 (3 mm ? 3 mm) fig 5. ball mapping for 3 mm ? 3 mm vfbga24 (transparent top view) PCAL6416APW int v dd(p) v dd(i2c-bus) sda reset scl p0_0 addr p0_1 p1_7 p0_2 p1_6 p0_3 p1_5 p0_4 p1_4 p0_5 p1_3 p0_6 p1_2 p0_7 p1_1 v ss p1_0 002aaf963 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 002aaf964 transparent top view p1_3 p0_4 p0_5 p1_4 p0_3 p1_5 p0_2 p1_6 p0_1 p1_7 p0_0 addr p0_6 p0_7 v ss p1_0 p1_1 p1_2 reset v dd(i2c-bus) int v dd(p) sda scl terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 7 8 9 10 11 12 24 23 22 21 20 19 pcal6416ahf 002aaf966 pcal6416aev transparent top view d b e c a ball a1 index area 12345 p0_0 reset sda scl 12345 p0_2 v dd(i2c-bus) v dd(p) addr a b p0_3 p0_4 p0_1 p1_7 p1_6 c p0_5 p1_2 p1_4 p1_5 d p0_6 v ss p1_0 p1_1 p1_3 e p0_7 002aag244 int
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 6 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander an empty cell indicates no ball is populated at that grid point. fig 6. pin configuration for xfbga24 (2 mm ? 2 mm) fig 7. ball mapping for 2 mm ? 2 mm xfbga24 (transparent top view) pcal6416aex transparent top view e d c b a 24 135 ball a1 index area 002aah190 p1_6 reset sda scl 12345 p0_0 v dd(i2c-bus) v dd(p) addr a b p0_2 p0_3 p0_1 p1_7 p1_5 c p0_4 p1_0 p1_4 p1_3 d p0_5 v ss p0_6 p1_1 p1_2 e p0_7 002aah145 int
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 7 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 5.2 pin description [1] pins p0_0 to p0_7 correspond to bits p0.0 to p0.7. at power-on, all i/o are configured as input. [2] pins p1_0 to p1_7 correspond to bits p1.0 to p1.7. at power-on, all i/o are configured as input. table 3. pin description symbol pin description tssop24 hwqfn24 vfbga24 xfbga24 int 1 22 a3 b3 interrupt output. connect to v dd(i2c-bus) or v dd(p) through a pull-up resistor. v dd(i2c-bus) 2 23 b3 a2 supply voltage of i 2 c-bus. connect directly to the v dd of the external i 2 c master. provides voltage-level translation. reset 3 24 a2 a1 active low reset input. connect to v dd(i2c-bus) through a pull-up resistor if no active connection is used. p0_0 [1] 4 1 a1 b1 port 0 input/output 0. p0_1 [1] 5 2 c3 c3 port 0 input/output 1. p0_2 [1] 6 3 b1 c1 port 0 input/output 2. p0_3 [1] 7 4 c1 c2 port 0 input/output 3. p0_4 [1] 8 5 c2 d1 port 0 input/output 4. p0_5 [1] 9 6 d1 e1 port 0 input/output 5. p0_6 [1] 10 7 e1 e2 port 0 input/output 6. p0_7 [1] 11 8 d2 d2 port 0 input/output 7. v ss 12 9 e2 e3 ground. p1_0 [2] 13 10 e3 d3 port 1 input/output 0. p1_1 [2] 14 11 e4 e4 port 1 input/output 1. p1_2 [2] 15 12 d3 e5 port 1 input/output 2. p1_3 [2] 16 13 e5 d5 port 1 input/output 3. p1_4 [2] 17 14 d4 d4 port 1 input/output 4. p1_5 [2] 18 15 d5 c5 port 1 input/output 5. p1_6 [2] 19 16 c5 c4 port 1 input/output 6. p1_7 [2] 20 17 c4 b5 port 1 input/output 7. addr 21 18 b5 a5 address input. connect directly to v dd(p) or ground. scl 22 19 a5 a4 serial clock bus. connect to v dd(i2c-bus) through a pull-up resistor. sda 23 20 a4 b4 serial data bus. connect to v dd(i2c-bus) through a pull-up resistor. v dd(p) 24 21 b4 a3 supply voltage of pcal6416a for port p.
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 8 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 6. voltage translation ta b l e 4 shows how to set up v dd levels for the necessary voltage translation between the i 2 c-bus and the pcal6416a. table 4. voltage translation v dd(i2c-bus) (sda and scl of i 2 c master) v dd(p) (port p) 1.8v 1.8v 1.8v 2.5v 1.8v 3.3v 1.8v 5v 2.5v 1.8v 2.5v 2.5v 2.5v 3.3v 2.5v 5v 3.3v 1.8v 3.3v 2.5v 3.3v 3.3v 3.3v 5v 5v 1.8v 5v 2.5v 5v 3.3v 5v 5v
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 9 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 7. functional description refer to figure 1 ? block diagram of pcal6416a (positive logic) ? . 7.1 device address the address of the pcal6416a is shown in figure 8 . addr is the hardware address package pin and is held to either high (logic 1) or low (logic 0) to assign one of the two possible sl ave addresses. the last bit of the slave address (r/w ) defines the operation (read or write) to be performed. a high (logic 1) selects a read operation, while a low (logic 0) selects a write operation. 7.2 interface definition 7.3 pointer register and command byte following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the pointer register in the pcal6416a. the lower three bits of this data byte state the operation (re ad or write) and the internal registers (input, output, polarity inversion, or configuration) that will be affe cted. bit 6 in conjunction with the lower three bits of the command byte are used to point to the extended features of the device (agile io). this register is write only. fig 8. pcal6416a address r/w 002aah045 0 1 0 0 0 0 ad dr fixed slave address hardware selectable table 5. interface definition byte bit 7 (msb) 6 5 4 3 2 1 0 (lsb) i 2 c-bus slave address l h l l l l addr r/w i/o data bus p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 fig 9. pointer register bits 002aaf540 b7 b6 b5 b4 b3 b2 b1 b0
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 10 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander [1] undefined. table 6. command byte pointer register bits command byte (hexadecimal) register protocol power-up default b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 00h input port 0 read byte xxxx xxxx [1] 0 0 0 0 0 0 0 1 01h input port 1 read byte xxxx xxxx 0 0 0 0 0 0 1 0 02h output port 0 read/write byte 1111 1111 0 0 0 0 0 0 1 1 03h output port 1 read/write byte 1111 1111 0 0 0 0 0 1 0 0 04h polarity inversion port 0 read/write byte 0000 0000 0 0 0 0 0 1 0 1 05h polarity inversion port 1 read/write byte 0000 0000 0 0 0 0 0 1 1 0 06h configuration port 0 read/write byte 1111 1111 0 0 0 0 0 1 1 1 07h configuration port 1 read/write byte 1111 1111 0 1 0 0 0 0 0 0 40h output drive strength register 0 read/write byte 1111 1111 0 1 0 0 0 0 0 1 41h output drive strength register 0 read/write byte 1111 1111 0 1 0 0 0 0 1 0 42h output drive strength register 1 read/write byte 1111 1111 0 1 0 0 0 0 1 1 43h output drive strength register 1 read/write byte 1111 1111 0 1 0 0 0 1 0 0 44h input latch regist er 0 read/write byte 0000 0000 0 1 0 0 0 1 0 1 45h input latch regist er 1 read/write byte 0000 0000 0 1 0 0 0 1 1 0 46h pull-up/pull-down enable register 0 read/write byte 0000 0000 0 1 0 0 0 1 1 1 47h pull-up/pull-down enable register 1 read/write byte 0000 0000 0 1 0 0 1 0 0 0 48h pull-up/pull-down selection register 0 read/write byte 1111 1111 0 1 0 0 1 0 0 1 49h pull-up/pull-down selection register 1 read/write byte 1111 1111 0 1 0 0 1 0 1 0 4ah interrupt mask r egister 0 read/write byte 1111 1111 0 1 0 0 1 0 1 1 4bh interrupt mask r egister 1 read/write byte 1111 1111 0 1 0 0 1 1 0 0 4ch interrupt status register 0 read byte 0000 0000 0 1 0 0 1 1 0 1 4dh interrupt status register 1 read byte 0000 0000 0 1 0 0 1 1 1 1 4fh output port configuration register read/write byte 0000 0000
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 11 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 7.4 register descriptions 7.4.1 input port register pair (00h, 01h) the input port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the configuration register. the input port registers are read only ; writes to these registers have no effect. the default value ?x? is determined by the externally applied logic level. an input port register read operation is performed as described in section 8.2 . 7.4.2 output port register pair (02h, 03h) the output port registers (registers 2 and 3) shows the outgoing logic levels of the pins defined as outputs by the configuration register. bit values in these registers have no effect on pins defined as inputs. in turn, reads from these registers reflect the value that was written to these registers, not the actual pin value. a register pair write operation is described in section 8.1 . a register pair read operation is described in section 8.2 . table 7. input port 0 register (address 00h) bit 7 6 5 4 3 2 1 0 symbol i0.7 i0.6 i0.5 i0.4 i0.3 i0.2 i0.1 i0.0 default xxxxxxxx table 8. input port 1 register (address 01h) bit 7 6 5 4 3 2 1 0 symbol i1.7 i1.6 i1.5 i1.4 i1.3 i1.2 i1.1 i1.0 default xxxxxxxx table 9. output port 0 register (address 02h) bit 7 6 5 4 3 2 1 0 symbol o0.7 o0.6 o0.5 o0.4 o0.3 o0.2 o0.1 o0.0 default 11111111 table 10. output port 1 register (address 03h) bit 7 6 5 4 3 2 1 0 symbol o1.7 o1.6 o1.5 o1.4 o1.3 o1.2 o1.1 o1.0 default 11111111
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 12 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 7.4.3 polarity inversion register pair (04h, 05h) the polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the configuration register. if a bit in these registers is set (written with ?1?), the corresponding port pin?s polarity is inverted in the input register. if a bit in this register is cleared (written with a ?0?), the corresponding po rt pin?s polarity is retained. a register pair write operation is described in section 8.1 . a register pair read operation is described in section 8.2 . 7.4.4 configuration register pair (06h, 07h) the configuration registers (registers 6 and 7) configure the direction of the i/o pins. if a bit in these registers is set to 1, the corresponding port pin is enabled as a high-impedance input. if a bit in these registers is cleared to 0, the corresponding port pin is enabled as an output. a register pair write operation is described in section 8.1 . a register pair read operation is described in section 8.2 . table 11. polarity inversion po rt 0 register (address 04h) bit 7 6 5 4 3 2 1 0 symbol n0.7 n0.6 n0.5 n0.4 n0.3 n0.2 n0.1 n0.0 default 00000000 table 12. polarity inversion port 1 register (address 05h) bit 7 6 5 4 3 2 1 0 symbol n1.7 n1.6 n1.5 n1.4 n1.3 n1.2 n1.1 n1.0 default 00000000 table 13. configuration port 0 register (address 06h) bit 7 6 5 4 3 2 1 0 symbol c0.7 c0.6 c0.5 c0.4 c0.3 c0.2 c0.1 c0.0 default 11111111 table 14. configuration port 1 register (address 07h) bit 7 6 5 4 3 2 1 0 symbol c1.7 c1.6 c1.5 c1.4 c1.3 c1.2 c1.1 c1.0 default 11111111
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 13 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 7.4.5 output drive strength register pairs (40h, 41h, 42h, 43h) the output drive strength registers control th e output drive level of the gpio. each gpio can be configured independently to a certain output current level by two register control bits. for example port 0.7 is controlled by register 41 cc0.7 (bits [7:6]), port 0.6 is controlled by register 41 cc0.6 (bits [5:4]). the output drive level of the gpio is programmed 00b = 0.25 ? , 01b = 0.5 ? , 10b = 0.75 ? or 11b = 1 ? of the drive capability of the i/o. see section 9.2 ? output drive strength control ? for more details. a register pair write operation is described in section 8.1 . a register pair read operation is described in section 8.2 . 7.4.6 input latch register pair (44h, 45h) the input latch registers (registers 44 and 45) enable and disable the input latch of the i/o pins. these registers are effective only when th e pin is configured as an input port. when an input latch register bit is 0, the correspon ding input pin state is not latched. a state change in the corresponding input pin generates an interrupt. a read of the input register clears the interrupt. if the input goes back to its initial logic state before the input port register is read, then the interrupt is cleared. when an input latch register bit is 1, the corresponding input pin state is latched. a change of state of the input generates an interrupt and the input logic value is loaded into the corresponding bit of the input port register (registers 0 and 1). a read of the input port register clears the interrupt. if the input pin returns to its initial logic state before the input port register is read, then the interrupt is no t cleared and the corresponding bit of the input port register keeps the logic value that initiated the interrupt. see figure 16 . for example, if the p0_4 input was as logic 0 and the input goes to logic 1 then back to logic 0, the input port 0 regist er will capture this change and an interrupt is generated (if unmasked). when the read is performed on the input port 0 register, the interrupt is table 15. current control port 0 register (address 40h) bit 7 6 5 4 3 2 1 0 symbol cc0.3 cc0.2 cc0.1 cc0.0 default 11111111 table 16. current control port 0 register (address 41h) bit 7 6 5 4 3 2 1 0 symbol cc0.7 cc0.6 cc0.5 cc0.4 default 11111111 table 17. current control port 1 register (address 42h) bit 7 6 5 4 3 2 1 0 symbol cc1.3 cc1.2 cc1.1 cc1.0 default 11111111 table 18. current control port 1 register (address 43h) bit 7 6 5 4 3 2 1 0 symbol cc1.7 cc1.6 cc1.5 cc1.4 default 11111111
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 14 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander cleared, assuming there were no additional input(s) that have changed, and bit 4 of the input port 0 register will read ?1?. the next read of the input port register bit 4 register should now read ?0?. an interrupt remains active when a non-latc hed input simultaneously switches state with a latched input and then returns to its original stat e. a read of the input register reflects only the change of state of the latched input and also clears the interrupt. the interrupt is not cleared if the input latch register changes from latched to non-latched configuration. if the input pin is changed from latched to non-latched input, a read from the input port register reflects the current port logic level. if the input pin is changed from non-latched to latched input, the read from the input register reflects the latched logic level. a register pair write operation is described in section 8.1 . a register pair read operation is described in section 8.2 . 7.4.7 pull-up/pull-down enable register pair (46h, 47h) these registers allow the user to enable or di sable pull-up/pull-down resistors on the i/o pins. setting the bit to logic 1 enables the sele ction of pull-up/pull-down resistors. setting the bit to logic 0 disconnects the pull-up/pull-down resistors from the i/o pins. also, the resistors will be disconnected when the outputs are configur ed as open-drain outputs (see section 7.4.11 ). use the pull-up/pull-down registers to select either a pull-up or pull-down resistor. a register pair write operation is described in section 8.1 . a register pair read operation is described in section 8.2 . table 19. input latch port 0 register (address 44h) bit 7 6 5 4 3 2 1 0 symbol l0.7 l0.6 l0.5 l0.4 l0.3 l0.2 l0.1 l0.0 default 00000000 table 20. input latch port 1 register (address 45h) bit 7 6 5 4 3 2 1 0 symbol l1.7 l1.6 l1.5 l1.4 l1.3 l1.2 l1.1 l1.0 default 00000000 table 21. pull-up/pull-down enable port 0 register (address 46h) bit 7 6 5 4 3 2 1 0 symbol pe0.7 pe0.6 pe0.5 pe0.4 pe0.3 pe0.2 pe0.1 pe0.0 default 00000000 table 22. pull-up/pull-down enable port 1 register (address 47h) bit 7 6 5 4 3 2 1 0 symbol pe1.7 pe1.6 pe1.5 pe1.4 pe1.3 pe1.2 pe1.1 pe1.0 default 00000000
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 15 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 7.4.8 pull-up/pull-down selection register pair (48h, 49h) the i/o port can be configured to have pull-up or pull-down resistor by programming the pull-up/pull-down selection register. setting a bit to logic 1 selects a 100 k ? pull-up resistor for that i/o pin. setting a bit to logic 0 selects a 100 k ? pull-down resistor for that i/o pin. if the pull-up/down feature is disconnec ted, writing to this register will have no effect on i/o pin. typical value is 100 k ? with minimum of 50 k ? and maximum of 150 k ? . a register pair write operation is described in section 8.1 . a register pair read operation is described in section 8.2 . 7.4.9 interrupt mask register pair (4ah, 4bh) interrupt mask registers are set to logic 1 upon power-on, disabling interrupts during system start-up. interrupts may be enabled by setting corresponding mask bits to logic 0. if an input changes state and the correspondin g bit in the interrupt mask register is set to 1, the interrupt is masked and the interrupt pin will not be asserted. if th e corresponding bit in the interrupt mask re gister is set to 0, the interrupt pin will be asserted. when an input changes state and the resulting interrupt is masked (interrupt mask bit is 1), setting the input mask register bit to 0 will cause the interrupt pi n to be asserted. if the interrupt mask bit of an input that is current ly the source of an interrupt is set to 1, the interrupt pin will be deassert ed. a register pair write operation is described in section 8.1 . a register pair read operation is described in section 8.2 . table 23. pull-up/pull-down selection port 0 register (address 48h) bit 7 6 5 4 3 2 1 0 symbol pud0.7 pud0.6 pud0.5 pud0.4 pud0.3 pud0.2 pud0.1 pud0.0 default 11111111 table 24. pull-up/pull-down selection port 1 register (address 49h) bit 7 6 5 4 3 2 1 0 symbol pud1.7 pud1.6 pud1.5 pud1.4 pud1.3 pud1.2 pud1.1 pud1.0 default 11111111 table 25. interrupt mask port 0 register (address 4ah) bit description bit 7 6 5 4 3 2 1 0 symbol m0.7 m0.6 m0.5 m0.4 m0.3 m0.2 m0.1 m0.0 default 11111111 table 26. interrupt mask port 1 register (address 4bh) bit description bit 7 6 5 4 3 2 1 0 symbol m1.7 m1.6 m1.5 m1.4 m1.3 m1.2 m1.1 m1.0 default 11111111
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 16 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 7.4.10 interrupt status register pair (4ch, 4dh) these read-only registers are used to identify the source of an interrupt. when read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. a logic 0 indicates that the input pin is not the source of an interrupt. when a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit will return logic 0. a register pair write operation is described in section 8.1 . a register pair read operation is described in section 8.2 . 7.4.11 output port configuration register (4fh) the output port configuration register select s port-wise push-pull or open-drain i/o stage. a logic 0 configures the i/o as push-pull (q1 and q2 are active, see figure 10 ). a logic 1 configures the i/o as open-drain (q1 is di sabled, q2 is active) and the recommended command sequence is to program this register (4fh) before the configuration register (06h and 07h) sets the port pins as outputs. oden0 configures port 0_x and oden1 configures port 1_x. 7.5 i/o port when an i/o is configured as an input, fets q1 and q2 are off, which creates a high-impedance input. the input voltage may be raised above v dd(p) to a maximum of 5.5 v. if the i/o is configured as an output, q1 or q2 is enabled, depending on the state of the output port register. in this case, there are low-impedance paths between the i/o pin and either v dd(p) or v ss . the external voltage applied to this i/o pin should not exceed the recommended levels for proper operation. table 27. interrupt status port 0 register (address 4ch) bit description bit 7 6 5 4 3 2 1 0 symbol s0.7 s0.6 s0.5 s0.4 s0.3 s0.2 s0.1 s0.0 default 00000000 table 28. interrupt status port 1 register (address 4dh) bit description bit 7 6 5 4 3 2 1 0 symbol s1.7 s1.6 s1.5 s1.4 s1.3 s1.2 s1.1 s1.0 default 00000000 table 29. output port configuration register (address 4fh) bit 7 6 5 4 3 2 1 0 symbol reserved oden1 oden0 default 00000000
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 17 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 7.6 power-on reset when power (from 0 v) is applied to v dd(p) , an internal power-on reset holds the pcal6416a in a reset condition until v dd(p) has reached v por . at that time, the reset condition is released and the pcal6416a registers and i 2 c-bus/smbus state machine initializes to their default states. after that, v dd(p) must be lowered to below v por and back up to the operating volt age for a power-reset cycle. see section 9.3 ? power-on reset requirements ? . 7.7 reset input (reset ) the reset input can be asserted to initialize the system while keeping the v dd(p) at its operating level. a reset can be accomplished by holding the reset pin low for a minimum of t w(rst) . the pcal6416a registers and i 2 c-bus/smbus state machine are changed to their default state once reset is low (0). when reset is high (1), the i/o levels at the p port can be changed externally or through the master. this input requires a pull-up resistor to v dd(i2c-bus) if no active connection is used. on power-up or reset, all registers return to default values. fig 10. simplified schematic of the i/ os (p0_0 to p0_7, p1_0 to p1_7) interrupt mask v dd(p) p0_0 to p0_7 p1_0 to p1_7 output port register data configuration register dq ck q data from shift register write configuration pulse output port register dq ck write pulse polarity inversion register dq ck data from shift register write polarity pulse input port register dq ck read pulse input port register data 002aag971 ff data from shift register ff ff ff q1 q2 v ss to int pull-up/pull-down control esd protection diode 100 k v dd(p) esd protection diode input port latch dq en latch read pulse input latch register dq ck ff data from shift register write input latch pulse
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 18 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 7.8 interrupt output (int ) an interrupt is generated by an y rising or falling edge of t he port inputs in the input mode. after time t v(int) , the signal int is valid. the interrupt is reset when data on the port changes back to the original value or when data is read from the port that generated the interrupt (see figure 16 ). resetting occurs in the read mode at the acknowledge (ack) or not acknowledge (nack) bit after the rising edge of the scl signal. interrupts that occur during the ack or nack clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. any change of the i/os after resetting is detected and is transmitted as int . a pin configured as an output cannot cause an interrupt. changing an i/o from an output to an input may cause a false interrupt to occu r, if the state of the pin does not match the contents of the input port register. the int output has an open-drain structur e and requires pull-up resistor to v dd(p) or v dd(i2c-bus) , depending on the application. int should be connected to the voltage source of the device that requires the interrupt information. when using the input latch feature, the input pin state is latched. the interrupt is reset only when data is read from the port that gener ated the interrupt. the reset occurs in the read mode at the acknowledge (ack) or not acknowledge (nack) bit after the rising edge of the scl signal. 8. bus transactions the pcal6416a is an i 2 c-bus slave device. data is exchanged between the master and pcal6416a through write and read commands using i 2 c-bus. the two communication lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up re sistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 8.1 write commands data is transmitted to the pcal6416a by sending the device address and setting the least significant bit (lsb) to a logic 0 (see figure 8 for device address). the command byte is sent after the address and determines which register receives the data that follows the command byte. twenty-two registers within the pcal6416a are configured to operate as eleven register pairs. the eleven pairs are input port, output por t, polarity inversion, configuration, output drive strength (two 16-bit registers), input latch, pull-up/pull-down enable, pull-up/pull-down selection, interrupt ma sk, and interrupt status registers. after sending data to one register, the next data byte is sent to the other register in the pair (see figure 11 and figure 12 ). for example, if the first byte is sent to output port 1 (register 3), the next byte is stored in output port 0 (register 2). there is no limit on the number of data bytes sent in one write transm ission. in this way, the host can continuously update a register pair independently of the other registers.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 19 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander fig 11. write to output port register 0 a s slave address start condition r/w acknowledge from slave 002aaf556 0000010 0 command byte a acknowledge from slave 12345678 scl 9 sda data 0 a write to port data out from port 0 t v(q) acknowledge from slave data 0 valid data to port 0 10000 ad dr 0 p stop condition 0.7 0.0 a acknowledge from slave data 1 t v(q) data 1 valid data to port 1 1.7 1.0 data out from port 1 fig 12. write to device registers 0 a s slave address start condition r/w acknowledge from slave 002aag972 1/0 0 0 1/0 1/0 1/0 1/0 0 command byte a acknowledge from slave 12345678 scl 9 sda data 0 a acknowledge from slave data to register 10000 ad dr 0 p stop condition msb lsb a acknowledge from slave data 1 data to register msb lsb
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 20 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 8.2 read commands to read data from the pcal6416a, the bus master must first send the pcal6416a address with the least significant bit set to a logic 0 (see figure 8 for device address). the command byte is sent after the address and determines which register is to be accessed. after a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. data from the register defined by the command byte is sent by the pcal6416a (see figure 13 and figure 16 ). data is clocked into the register on the rising edge of the ack clock pulse. after the first byte is read, additional bytes may be read, but the data now reflects the information in the other register in the pair. for example, if input port 1 is read, the next by te read is input port 0.there is no limit on the number of data bytes received in one read transmission, but on the final byte received the bus master must not acknowledge the data. after a subsequent restart, the command byte contains the value of the next register to be read in the pair. for example, if input port 1 was read last before the restart, the register that is read after the re start is the input port 0. fig 13. read from device registers 10000 ad dr 0 a s0 start condition r/w acknowledge from slave 002aah046 a acknowledge from slave sda a p acknowledge from master data from lower or upper byte of register data (first byte) slave address stop condition s (repeated) start condition (cont.) (cont.) 10000 ad dr 1 a 0 r/w acknowledge from slave slave address at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter na no acknowledge from master data from upper or lower byte of register data (last byte) msb lsb msb lsb 1/0 0 0 1/0 1/0 1/0 1/0 0 command byte
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 21 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander remark: transfer of data can be stopped at any moment by a stop conditi on. when this occurs, data present at the latest acknowledge pha se is valid (output mode). it is assumed that the command byte has previous ly been set to ?00? (read input port register). this figure eliminates the command byte transfers and a restar t between the initial slave address call and actual data transfer from p port (see figure 13 ). fig 14. read input port register (non-latched), scenario 1 10000 ad dr 1 a s0 start condition r/w acknowledge from slave 002aah143 a scl sda a read from port 0 p 987654321 i0.x slave address stop condition acknowledge from master a i1.x acknowledge from master a i0.x acknowledge from master 1 i1.x non acknowledge from master data into port 0 read from port 1 data into port 1 int 6543210 7 6543210 7 6543210 7 6543210 7 int t v(int) t rst(int)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 22 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander remark: transfer of data can be stopped at any moment by a stop conditi on. when this occurs, data present at the latest acknowledge pha se is valid (output mode). it is assumed that the command byte has previous ly been set to ?00? (read input port register). this figure eliminates the command byte transfers and a restar t between the initial slave address call and actual data transfer from p port (see figure 13 ). fig 15. read input port register (non-latched), scenario 2 10000 ad dr 1 a s0 start condition r/w acknowledge from slave 002aah144 a scl sda a read from port 0 p 987654321 i0.x slave address stop condition acknowledge from master a i1.x acknowledge from master a i0.x acknowledge from master 1 i1.x non acknowledge from master data into port 0 read from port 1 data into port 1 int t v(int) t rst(int) data 00 data 10 data 03 data 12 data 00 data 01 t h(d) t h(d) data 02 t su(d) data 03 t su(d) data 10 data 11 data 12
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 23 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander remark: transfer of data can be stopped at any moment by a stop conditi on. when this occurs, data present at the latest acknowledge pha se is valid (output mode). it is assumed that the command byte has previous ly been set to ?00? (read input port register). this figure eliminates the command byte transfers and a restar t between the initial slave address call and actual data transfer from p port (see figure 13 ). fig 16. read input port register (latch enabled), scenario 3 10000 ad dr 1 a s0 start condition r/w acknowledge from slave 002aah054 a scl sda a read from port 0 p 987654321 i0.x slave address stop condition acknowledge from master a i1.x acknowledge from master a i0.x acknowledge from master 1 i1.x non acknowledge from master data into port 0 read from port 1 data into port 1 int t v(int) t rst(int) data 01 data 10 data 02 data 11 data 01 t h(d) data 02 t su(d) data 01 data 10 data 11 data 10
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 24 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 9. application design-in information 9.1 minimizing i dd when the i/os are used to control leds when the i/os are used to control leds, they are normally connected to v dd through a resistor as shown in figure 17 . since the led acts as a diode, when the led is off the i/o v i is about 1.2 v less than v dd(p) . the supply current, i dd(p) , increases as v i becomes lower than v dd(p) . designs needing to minimize current consumpt ion, such as battery power applications, should consider maintaining the i/o pins greater than or equal to v dd when the led is off. figure 18 shows a high value resistor in parallel with the led. figure 19 shows v dd(p) less than the led supply voltage by at least 1.2 v. both of these methods maintain the i/o v i at or above v dd(p) and prevents additional supply cu rrent consumption when the led is off. device address configured as 0100 000x for this example. p0_0 and p0_2 through p1_0 are configured as inputs. p0_1 and p1_1 through p1_7 are configured as outputs. (1) external resistors are required for inputs (on p port) that ma y float. also, internal pull-up or pull-down may be used to eli minate the need for external components. if a driver to an input will never let the input float, a resistor is not needed. if an outpu t in the p port is configured as a push-pull output there is no need for ex ternal pull-up resistors. if an output in the p port is configu red as an open-drain output, external pull-up resistors are required. fig 17. typical application pcal6416a p0_0 p0_1 scl sda v dd scl sda p0_2 p0_3 gnd master controller gnd v dd(i2c-bus) = 1.8 v controlled switch a b enable int v dd(p) int 10 k subsystem 1 (e.g., alarm system) alarm (1) p0_4 p0_5 p0_6 p0_7 10 k 10 k reset reset v dd(p) 002aaf965 p1_0 p1_1 p1_2 p1_3 p1_4 p1_5 p1_6 p1_7 v dd(i2c-bus) v dd(i2c-bus) addr keypad 10 k 10 k (7)
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 25 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 9.2 output drive strength control the output drive strength registers allow the user to control the output drive level of the gpio. each gpio can be configured independe ntly to one of the four possible output current levels. by programming these bits the user is changing the number of transistor pairs or ?fingers? that drive the i/o pad. figure 20 shows a simplified output stage. the behavior of the pad is affected by the configuration register, the output port data, and the current control register. when the current control register bits are programmed to 10b, then only two of the fingers are active, reducing the current drive capability by 50 %. fig 18. high value resistor in parallel with the led fig 19. device supplied by a lower voltage 002aah278 led v dd(p) pn 100 k v dd 002aah279 led v dd(p) pn 3.3 v 5 v fig 20. simplified output stage v dd(p) p0_0 to p0_7 p1_0 to p1_7 configuration register 002aah053 decoder pmos_en0 pmos_en1 pmos_en2 pmos_en3 nmos_en3 nmos_en2 nmos_en1 nmos_en0 output port register current control register pmos_en[3:0] nmos_en[3:0]
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 26 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander reducing the current drive capa bility may be desirable to redu ce system noise. when the output switches (transitions from h/l), there is a peak curr ent that is a function of the output drive selection. this peak current runs through v dd and v ss package inductance and will create noise (some radi ated, but more critically simultaneous switching noise (ssn)). in other words, switching many outpu ts at the same time will create ground and supply noise. the output drive strength control through the output drive strength registers allows the user to mitigate ssn issu es without the need of additional external components. 9.3 power-on reset requirements in the event of a glitch or data corruption, pcal6416a can be reset to its default conditions by using the power-on reset feature. power-on reset requires that the device go through a power cycle to be completely reset. this reset also happens when the device is powered on for the first time in an application. the two types of power-on reset are shown in figure 21 and figure 22 . ta b l e 3 0 specifies the performance of the power- on reset feature for pcal6416a for both types of power-on reset. fig 21. v dd(p) is lowered below 0.2 v or to 0 v and then ramped up to v dd(p) fig 22. v dd(p) is lowered below the por threshold, then ramped back up to v dd(p) 002aag960 v dd(p) time ramp-up ramp-down (dv/dt) r (dv/dt) f re-ramp-up (dv/dt) r time to re-ramp when v dd(p) drops below 0.2 v or to v ss t d(rst) 002aag961 v dd(p) time ramp-down (dv/dt) f ramp-up (dv/dt) r time to re-ramp when v dd(p) drops to v por(min) ? 50 mv t d(rst) v i drops below por levels
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 27 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander [1] level that v dd(p) can glitch down to with a ramp rate = 0.4 ? s/v, but not cause a functional disruption when t w(gl)vdd <1 ? s. [2] glitch width that will not cause a functional disruption when ? v dd(gl) =0.5 ? v dd(p) . glitches in the power supply can also affect the power-on reset performance of this device. the glitch width (t w(gl)vdd ) and glitch height ( ? v dd(gl) ) are dependent on each other. the bypass capacitance, source impedan ce, and device impedance are factors that affect power-on reset performance. figure 23 and ta b l e 3 0 provide more information on how to measure thes e specifications. v por is critical to the power-on reset. v por is the voltage level at which the reset condition is released and all the registers and the i 2 c-bus/smbus state machine are initialized to their default states. the value of v por differs based on the v dd(p) being lowered to or from 0v. figure 24 and ta b l e 3 0 provide more details on this specification. table 30. recommended supply sequencing and ramp rates t amb =25 ? c (unless otherwise noted). not tested; specified by design. symbol parameter condition min typ max unit (dv/dt) f fall rate of change of voltage figure 21 0.1 - 2000 ms (dv/dt) r rise rate of change of voltage figure 21 0.1 - 2000 ms t d(rst) reset delay time figure 21 ; re-ramp time when v dd(p) drops below 0.2 v or to v ss ) 1- - ? s figure 22 ; re-ramp time when v dd(p) drops to v por(min) ? 50 mv) 1- - ? s ? v dd(gl) glitch supply voltage difference figure 23 [1] --1.0v t w(gl)vdd supply voltage glitch pulse width figure 23 [2] --10 ? s v por(trip) power-on reset trip voltage falling v dd(p) 0.7 - - v rising v dd(p) --1.4v fig 23. glitch width and glitch height fig 24. power-on reset voltage (v por ) 002aag962 v dd(p) time t w(gl)vdd ?v dd(gl) 002aag963 por time v dd(p) time v por (rising v dd(p) ) v por (falling v dd(p) )
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 28 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 9.4 device current consumption with internal pull-up and pull-down resistors the pcal6416a integrates programmable pull-up and pull-down resistors to eliminate external components when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is driving the inputs to the power supply rails. since these pull-up and pull-down resistors are in ternal to the device itself, they contribute to the current consumption of the device and must be considered in the overall system design. the pull-up or pull-down function is selected in registers 48h and 49h, while the resistor is connected by the enable registers 46h and 47 h. the configuration of the resistors is shown in figure 10 . if the resistor is configured as a pull-up, that is, connected to v dd , a current will flow from the v dd(p) pin through the resistor to ground when the pin is held low. this current will appear as additional i dd upsetting any current consumption measurements. in the same manner, if the resistor is config ured as a pull-down and the pin is held high, current will flow from the power su pply through the pin to the v ss pin. while this current will not be measured as part of i dd , one must be mindful of the 200 ma limiting value through v ss . the pull-up and pull-down resistors are simple resistors and the current is linear with voltage. the resistance specification for these devices spans from 50 k ? with a nominal 100 k ? value. any current flow through these resi stors is additive by the number of pins held high or low and the current can be calculated by ohm?s law. see figure 28 for a graph of supply current versus the number of pull-up resistors. 9.5 i 2 c-bus error recovery techniques there are a number of techniques to recover from error conditions on the i 2 c-bus. slave devices like the pcal6416a use a state machine to implement the i 2 c protocol and expect a certain sequence of events to occur to function properly. unexpected events at the i 2 c master can wreak havoc with the slaves connected on the bus. however, it is usually possible to recover deterministically to a known bus state with careful protocol manipulation. a hard slave reset, either through power-on reset or by activating the reset pin, will set the device back into the default state. of co urse, this means the input/output pins and their configuration will be lost, whic h might cause some system issues. a stop condition, which is only initiated by the master, will reset th e slave state machine into a known condition where sda is not driven low by the slave and logically, the slave is waiting for a start condition. a stop condition is defined as sda transitioning from low to high while scl is high. if the master is interrupted during a packet transmission, the slave may be sending data or performing an acknowledge, driving the i 2 c-bus sda line low. since sda is low, it effectively blocks any other i 2 c-bus transaction. a determin istic method to clear this situation, once the master recognizes a ?stu ck bus? state, is for th e master to blindly transmit nine clocks on scl. if the slave was transmitting da ta or acknowledging, nine or
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 29 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander more clocks ensures the slave state machine returns to a kn own, idle state since the protocol calls for eight data bits and one ack bit. it does not matter when the slave state machine finishes its transmission, extra cloc ks will be recognized as stop conditions. the pcal6416a scl pin is an input only. if scl is stuck low, then only the bus master or a slave performing a clock stretch operation can cause this condition. with careful design of the bus mast er error recovery firmware, many i 2 c-bus protocol problems can be avoided. 10. limiting values [1] the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. table 31. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd(i2c-bus) i 2 c-bus supply voltage ? 0.5 +6.5 v v dd(p) supply voltage port p ? 0.5 +6.5 v v i input voltage [1] ? 0.5 +6.5 v v o output voltage [1] ? 0.5 +6.5 v i ik input clamping current addr, reset , scl; v i <0v - ? 20 ma i ok output clamping current int ; v o <0v - ? 20 ma i iok input/output clamping current p port; v o <0v or v o >v dd(p) - ? 20 ma sda; v o <0v or v o >v dd(i2c-bus) - ? 20 ma i ol low-level output current continuous; p port; v o = 0 v to v dd(p) -50ma continuous; sda, int ; v o = 0 v to v dd(i2c-bus) -25ma i oh high-level output current continuous; p port; v o = 0 v to v dd(p) -25ma i dd supply current continuous through v ss - 200 ma i dd(p) supply current port p continuous through v dd(p) - 160 ma i dd(i2c-bus) i 2 c-bus supply current continuous through v dd(i2c-bus) -10ma t stg storage temperature ? 65 +150 ?c t j(max) maximum junction temperature - 125 ?c
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 30 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 11. recommended operating conditions 12. thermal characteristics [1] the package thermal impedance is calc ulated in accordance with jesd 51-7. table 32. operating conditions symbol parameter conditions min max unit v dd(i2c-bus) i 2 c-bus supply voltage 1.65 5.5 v v dd(p) supply voltage port p 1.65 5.5 v v ih high-level input vo ltage scl, sda, reset 0.7 ? v dd(i2c-bus) 5.5 v addr, p1_7 to p0_0 0.7 ? v dd(p) 5.5 v v il low-level input voltage scl, sda, reset ? 0.5 0.3 ? v dd(i2c-bus) v addr, p1_7 to p0_0 ? 0.5 0.3 ? v dd(p) v i oh high-level output current p1_7 to p0_0 - 10 ma i ol low-level output current p1_7 to p0_0 - 25 ma t amb ambient temperature operating in free air ? 40 +85 ?c table 33. thermal characteristics symbol parameter conditions max unit z th(j-a) transient thermal impedance from junction to ambient tssop24 package [1] 88 k/w hwqfn24 package [1] 66 k/w vfbga24 package [1] 171 k/w
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 31 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 13. static characteristics table 34. static characteristics t amb = ? 40 ? c to +85 ? c; v dd(i2c-bus) = 1.65 v to 5.5 v; unless otherwise specified. symbol parameter conditions min typ [1] max unit v ik input clamping voltage i i = ? 18 ma ? 1.2 - - v v por power-on reset voltage v i =v dd(p) or v ss ; i o =0ma - 1.1 1.4 v v oh high-level output voltage [2] p port; i oh = ? 8 ma; ccx.x = 11b v dd(p) =1.65v 1.2 - - v v dd(p) = 2.3 v 1.8 - - v v dd(p) =3v 2.6 - - v v dd(p) = 4.5 v 4.1 - - v p port; i oh = ? 2.5 ma and ccx.x = 00b; i oh = ? 5 ma and ccx.x = 01b; i oh = ? 7.5 ma and ccx.x = 10b; i oh = ? 10 ma and ccx.x = 11b; v dd(p) =1.65v 1.1 - - v v dd(p) = 2.3 v 1.7 - - v v dd(p) =3v 2.5 - - v v dd(p) = 4.5 v 4.0 - - v v ol low-level output voltage [2] p port; i ol = 8 ma; ccx.x = 11b v dd(p) = 1.65 v - - 0.45 v v dd(p) =2.3v - - 0.25 v v dd(p) =3v - - 0.25 v v dd(p) =4.5v - - 0.2 v p port; i ol = 2.5 ma and ccx.x = 00b; i ol = 5 ma and ccx.x = 01b; i ol = 7.5 ma and ccx.x = 10b; i ol = 10 ma and ccx.x = 11b; v dd(p) =1.65v - - 0.5 v v dd(p) =2.3v - - 0.3 v v dd(p) =3v - - 0.25 v v dd(p) =4.5v - - 0.2 v i ol low-level output current [3] v ol = 0.4 v; v dd(p) =1.65v to 5.5v sda 3 - - ma int 315 [4] -ma i i input current v dd(p) = 1.65 v to 5.5 v scl, sda, reset ; v i =v dd(i2c-bus) or v ss -- ? 1 ? a addr; v i =v dd(p) or v ss -- ? 1 ? a i ih high-level input current p port; v i =v dd(p) ; v dd(p) = 1.65 v to 5.5 v - - 1 ? a i il low-level input current p port; v i =v ss ; v dd(p) = 1.65 v to 5.5 v - - 1 ? a
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 32 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander i dd supply current i dd(i2c-bus) +i dd(p) ; sda, p port, addr, reset ; v i on sda and reset =v dd(i2c-bus) or v ss ; v i on p port and addr = v dd(p) ; i o =0ma;i/o=inputs; f scl = 400 khz v dd(p) = 3.6 v to 5.5 v - 10 25 ? a v dd(p) = 2.3 v to 3.6 v - 6.5 15 ? a v dd(p) = 1.65 v to 2.3 v - 4 9 ? a i dd(i2c-bus) +i dd(p) ; scl, sda, p port, addr, reset ; v i on scl, sda and reset =v dd(i2c-bus) or v ss ; v i on p port and addr = v dd(p) ; i o =0ma;i/o=inputs; f scl = 0 khz v dd(p) = 3.6 v to 5.5 v - 1.5 7 ? a v dd(p) = 2.3 v to 3.6 v - 1 3.2 ? a v dd(p) = 1.65 v to 2.3 v - 0.5 1.7 ? a active mode; i dd(i2c-bus) +i dd(p) ; p port, addr, reset ; v i on reset =v dd(i2c-bus) ; v i on p port and addr = v dd(p) ; i o =0ma;i/o=inputs; f scl = 400 khz, continuous register read v dd(p) = 3.6 v to 5.5 v - 60 125 ? a v dd(p) = 2.3 v to 3.6 v - 40 75 ? a v dd(p) = 1.65 v to 2.3 v - 20 45 ? a with pull-ups enabled (pcal6416a only); i dd(i2c-bus) +i dd(p) ; p port, addr, reset ; v i on scl, sda and reset =v dd(i2c-bus) or v ss ; v i on p port = v ss ; v i on addr = v dd(i2c-bus) or v ss ; i o = 0 ma; i/o = inputs with pull-up enabled; f scl =0khz v dd(p) = 1.65 v to 5.5 v - 1.1 1.5 ma ? i dd additional quiescent supply current [5] scl, sda, reset ; one input at v dd(i2c-bus) ? 0.6 v, other inputs at v dd(i2c-bus) or v ss ; v dd(p) =1.65vto5.5v -- 25 ? a p port, addr; one input at v dd(p) ? 0.6 v, other inputs at v dd(p) or v ss ; v dd(p) =1.65vto5.5v -- 80 ? a c i input capacitance v i =v dd(i2c-bus) or v ss ; v dd(p) = 1.65 v to 5.5 v - 6 7 pf c io input/output capacitance v i/o =v dd(i2c-bus) or v ss ; v dd(p) =1.65vto5.5v - 7 8 pf v i/o =v dd(p) or v ss ; v dd(p) = 1.65 v to 5.5 v - 7.5 8.5 pf r pu(int) internal pull-up resistance input/output 50 100 150 k ? r pd(int) internal pull-down resistance input/output 50 100 150 k ? table 34. static characteristics ?continued t amb = ? 40 ? c to +85 ? c; v dd(i2c-bus) = 1.65 v to 5.5 v; unless otherwise specified. symbol parameter conditions min typ [1] max unit
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 33 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander [1] for i dd , all typical values are at nominal supply voltage (1.8 v, 2.5 v, 3.3 v, 3.6 v or 5 v v dd ) and t amb =25 ? c. except for i dd , the typical values are at v dd(p) =v dd(i2c-bus) = 3.3 v and t amb =25 ? c. [2] the total current sourced by all i/os must be limited to 160 ma. [3] each i/o must be externally limited to a maximum of 25 ma and each octal (p0_0 to p0_7 and p1_0 to p1_7) must be limited to a maximum current of 100 ma, for a device total of 200 ma. [4] typical value for t amb =25 ? c. v ol = 0.4 v and v dd(i2c-bus) =v dd(p) = 3.3 v. typical value for v dd(i2c-bus) =v dd(p) < 2.5 v, v ol =0.6v. [5] internal pull-up/pull-down resistors disabled. 13.1 typical characteristics i dd =i dd(i2c-bus) + i dd(p) fig 25. supply current versus ambient temperature fig 26. standby supply current versus ambient temperature t amb =25 ? c i dd =i dd(i2c-bus) + i dd(p) fig 27. supply current versus supply voltage fig 28. supply current versus number of i/o held low 8 12 4 16 20 i dd (a) 0 t amb (c) ?40 85 60 10 35 ?15 002aag973 v dd(p) = 5.5 v 5.0 v 3.6 v 3.3 v 2.5 v 2.3 v v dd(p) = 1.8 v 1.65 v 600 800 400 1400 i dd(stb) (na) 0 t amb (c) ?40 85 60 10 35 ?15 002aag974 v dd(p) = 5.5 v 5.0 v 3.6 v 3.3 v 200 1000 2.5 v 2.3 v 1.8 v 1.65 v 8 12 4 16 20 i dd (a) 0 v dd(p) (v) 1.5 5.5 4.5 2.5 3.5 002aag975 0.4 0.8 1.2 i dd(p) (ma) 0 number of i/o held low 016 12 48 002aah201 t amb = ?40 c 25 c 85 c
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 34 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander a. v dd(p) =1.65v b. v dd(p) =1.8v c. v dd(p) =2.5v d. v dd(p) =3.3v e. v dd(p) =5.0v f. v dd(p) =5.5v fig 29. i/o sink current versus low-level output voltage with ccx.x = 11b v ol (v) 0 0.3 0.2 0.1 002aaf578 15 25 35 i sink (ma) 0 t amb = ?40 c 25 c 85 c 5 10 20 30 v ol (v) 0 0.3 0.2 0.1 002aaf579 15 25 35 i sink (ma) 0 t amb = ?40 c 25 c 85 c 5 10 20 30 v ol (v) 0 0.3 0.2 0.1 002aaf580 20 50 i sink (ma) 0 t amb = ?40 c 25 c 85 c 10 30 40 v ol (v) 0 0.3 0.2 0.1 002aaf581 20 40 60 i sink (ma) 0 t amb = ?40 c 25 c 85 c v ol (v) 0 0.3 0.2 0.1 002aaf582 30 50 70 i sink (ma) 0 t amb = ?40 c 25 c 85 c 10 20 40 60 v ol (v) 0 0.3 0.2 0.1 002aaf583 30 50 70 i sink (ma) 0 t amb = ?40 c 25 c 85 c 10 20 40 60
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 35 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander a. v dd(p) =1.65v b. v dd(p) =1.8v c. v dd(p) =2.5v d. v dd(p) =3.3v e. v dd(p) =5.0v f. v dd(p) =5.5v fig 30. i/o source current versus high-level output voltage with ccx.x = 11b v dd(p) ? v oh (v) 0 0.6 0.4 0.2 002aaf561 10 20 30 i source (ma) 0 t amb = ?40 c 25 c 85 c v dd(p) ? v oh (v) 0 0.6 0.4 0.2 002aaf562 15 25 35 i source (ma) 0 t amb = ?40 c 25 c 85 c 5 10 20 30 v dd(p) ? v oh (v) 0 0.6 0.4 0.2 002aaf563 20 40 60 i source (ma) 0 t amb = ?40 c 25 c 85 c v dd(p) ? v oh (v) 0 0.6 0.4 0.2 002aaf564 30 50 70 i source (ma) 0 t amb = ?40 c 25 c 85 c 10 20 40 60 v dd(p) ? v oh (v) 0 0.6 0.4 0.2 002aaf565 30 60 90 i source (ma) 0 t amb = ?40 c 25 c 85 c v dd(p) ? v oh (v) 0 0.6 0.4 0.2 002aaf566 30 60 90 i source (ma) 0 t amb = ?40 c 25 c 85 c
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 36 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander (1) v dd(p) = 1.8 v; i sink =10ma (2) v dd(p) = 5 v; i sink =10ma (3) v dd(p) = 1.8 v; i sink =1ma (4) v dd(p) = 5 v; i sink =1ma i source = ? 10 ma fig 31. low-level output voltage versus temperature with ccx.x = 11b fig 32. i/o high voltage versus temperature with ccx.x = 11b 60 80 20 100 120 v ol (mv) 0 t amb (c) ?40 85 60 10 35 ?15 002aah056 (1) (3) (4) (2) 40 t amb (c) ?40 85 60 10 35 ?15 002aah057 160 120 200 0 v dd(p) ? v oh (mv) v dd(p) = 1.8 v 5 v 80 40
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 37 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 14. dynamic characteristics [1] minimum time for sda to become high or minimum time to wait before doing a start. table 35. i 2 c-bus interface timing requirements over recommended operating free air temperat ure range, unless otherwise specified. see figure 34 . symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max f scl scl clock frequency 0 100 0 400 khz t high high period of the scl clock 4 - 0.6 - ? s t low low period of the scl clock 4.7 - 1.3 - ? s t sp pulse width of spikes that must be suppressed by the input filter 0 50 0 50 ns t su;dat data set-up time 250 - 100 - ns t hd;dat data hold time 0 - 0 - ns t r rise time of both sda and scl signals - 1000 20 300 ns t f fall time of both sda and scl signals - 300 20 ? (v dd /5.5v) 300 ns t buf bus free time between a stop and start condition 4.7 - 1.3 - ? s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - ? s t hd;sta hold time (repeated) start condition 4 - 0.6 - ? s t su;sto set-up time for stop condition 4 - 0.6 - ? s t vd;dat data valid time scl low to sda output valid -3.45 - 0.9 ? s t vd;ack data valid acknowledge time ack signal from scl low to sda (out) low -3.45 - 0.9 ? s table 36. reset timing requirements over recommended operating free air temperat ure range, unless otherwise specified. see figure 36 . symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max t w(rst) reset pulse width 30 - 30 - ns t rec(rst) reset recovery time 200 - 200 - ns t rst reset time [1] 600 - 600 - ns
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 38 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 15. parameter measure ment information table 37. switching characteristics over recommended operating free air temperature range; c l ? 100 pf; unless other wise specified. see figure 35 . symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max t v(int) valid time on pin int from p port to int -1-1 ? s t rst(int) reset time on pin int from scl to int -1-1 ? s t v(q) data output valid time from scl to p port - 400 - 400 ns t su(d) data input set-up time from p port to scl 0 - 0 - ns t h(d) data input hold time from p port to scl 300 - 300 - ns a. sda load configuration b. transaction format c. voltage waveforms c l includes probe and jig capacitance. all inputs are supplied by generators havi ng the following characteristics: prr ? 10 mhz; z o =50 ? ; t r /t f ? 30 ns. all parameters and waveforms ar e not applicable to all devices. byte 1 = i 2 c-bus address; byte 2, byte 3 = p port data. (1) see figure 16 . fig 33. i 2 c-bus interface load circuit and voltage waveforms 002aag977 dut c l = 50 pf r l = 1 k sda v dd(i2c-bus) stop condition (p) data bit 0 (lsb) data bit 7 (msb) ack (a) r/w bit 0 (lsb) address bit 1 address bit 7 (msb) start condition (s) stop condition (p) two bytes for read input port register (1) 002aag952 t low t high t r t f 0.7 v dd(i2c-bus) 0.3 v dd(i2c-bus) 0.7 v dd(i2c-bus) 0.3 v dd(i2c-bus) t sp t buf t f t hd;sta t r scl sda t su;dat t hd;dat t f(o) t vd;ack t vd;dat t vd;ack t su;sta t su;sto 002aag978 repeat start condition stop condition
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 39 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander a. interrupt load configuration b. voltage waveforms c l includes probe and jig capacitance. all inputs are supplied by generators havi ng the following characteristics: prr ? 10 mhz; z o =50 ? ; t r /t f ? 30 ns. all parameters and waveforms ar e not applicable to all devices. fig 34. interrupt load circuit and voltage waveforms 002aag979 dut c l = 100 pf r l = 4.7 k int v dd(i2c-bus) 10000 ad dr 1 a s0 slave address start condition r/w acknowledge from slave 002aag980 8 bits (one data byte) from port a acknowledge from slave sda 1 no acknowledge from master data into port data from port data 1 data 2 int data 2 data 1 p stop condition t v(int) t rst(int) t su(d) 12345678 scl 9 address t rst(int) a a view a - a int pn t v(int) 0.5 v dd(i2c-bus) 0.5 v dd(p) view b - b scl 0.5 v dd(i2c-bus) int r/w a t rst(int) 0.3 v dd(i2c-bus) 0.7 v dd(i2c-bus) b b
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 40 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander a. p port load configuration b. write mode (r/w =0) c. read mode (r/w =1) c l includes probe and jig capacitance. t v(q) is measured from 0.7 ? v dd on scl to 50 % i/o (pn) output. all inputs are supplied by generators havi ng the following characteristics: prr ? 10 mhz; z o =50 ? ; t r /t f ? 30 ns. the outputs are measured one at a time, with one transition per measurement. all parameters and waveforms ar e not applicable to all devices. fig 35. p port load circuit and voltage waveforms 002aag981 dut c l = 50 pf 500 pn 2 v dd(p) 500 002aag982 scl sda p0 a t v(q) 0.3 v dd(i2c-bus) 0.7 v dd(i2c-bus) p7 last stable bit unstable data pn 002aag983 scl pn p0 a t h(d) 0.3 v dd(i2c-bus) 0.7 v dd(i2c-bus) p7 0.5 v dd(p) t su(d)
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 41 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander a. sda load configuration b. p port load configuration c. reset timing c l includes probe and jig capacitance. all inputs are supplied by generators havi ng the following characteristics: prr ? 10 mhz; z o =50 ? ; t r /t f ? 30 ns. the outputs are measured one at a time, with one transition per measurement. i/os are configured as inputs. all parameters and waveforms ar e not applicable to all devices. fig 36. reset load circuits and voltage waveforms 002aag977 dut c l = 50 pf r l = 1 k sda v dd(i2c-bus) 002aag981 dut c l = 50 pf 500 pn 2 v dd(p) 500 sda scl 002aag984 t rst t rec(rst) t w(rst) reset pn start t rst ack or read cycle 0.3 v dd(i2c-bus) 0.5 v dd(i2c-bus) 0.5 v dd(p) t rec(rst)
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 42 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 16. package outline fig 37. package outline sot994-1 (hwqfn24) references outline version european projection issue date iec jedec jeita sot994-1 - - - mo-220 - - - sot994-1 07-02-07 07-03-03 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. unit a (1) max mm 0.8 0.05 0.00 0.30 0.18 4.1 3.9 2.25 1.95 4.1 3.9 2.25 1.95 2.5 2.5 0.1 a 1 dimensions (mm are the original dimensions) hwqfn24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.75 mm 0 2.5 5 mm scale b c 0.2 d (1) d h e (1) e h e 0.5 e 1 e 2 l 0.5 0.3 v w 0.05 y 0.05 y 1 0.1 b a terminal 1 index area e d detail x a a 1 c b e 2 e 1 e e 1/2 e 1/2 e ac b ? v m c ? w m terminal 1 index area 6 13 12 7 18 24 19 1 l e h d h c y c y 1 x
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 43 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander fig 38. package outline sot355-1 (tssop24) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 0.4 0.3 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot355-1 mo-153 99-12-27 03-02-19 0.25 0.5 0.2 w m b p z e 11 2 24 13 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 a max. 1.1
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 44 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander fig 39. package outline sot1199-1 (vfbga24) references outline version european projection issue date iec jedec jeita sot1199-1 - - - sot1199-1_po 11-02-16 12-03-13 unit mm max nom min 1.00 0.85 0.75 0.25 0.20 0.15 0.35 0.30 0.25 3.1 3.0 2.9 3.1 3.0 2.9 0.5 2 0.15 0.08 a dimensions vfbga24: plastic very thin fine-pitch ball grid array package; 24 balls; body 3 x 3 x 0.85 mm sot1199-1 a 1 a 2 0.75 0.65 0.60 bdeee 1 2 e 2 vw 0.05 yy 1 0.1 0 1 2 mm scale ball a1 index area b a d e x c y c y 1 detail x a a 1 a 2 a b c d e 12345 b e 2 e 1 e e ac b ? v c ? w ball a1 index area
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 45 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander fig 40. package outline sot1342-1 (xfbga24)

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pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 46 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 17. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 17.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 17.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 47 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 17.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 41 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 3 8 and 39 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 41 . table 38. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 39. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 48 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 41. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 49 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 18. soldering: pcb footprints fig 42. pcb footprint for sot355-1 (tssop24); reflow soldering dimensions in mm ay by d1 d2 gy hy p1 c gx sot355-1_fr hx sot355-1 solder land occupied area footprint information for reflow soldering of tssop24 package ay by gy c hy hx gx p1 generic footprint pattern refer to the package outline drawing for actual layout p2 (0.125) (0.125) d1 d2 (4x) p2 7.200 4.500 1.350 0.400 0.600 8.200 5.300 7.450 8.600 0.650 0.750
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 50 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander fig 43. pcb footprint for sot994-1 (hwqfn24); reflow soldering sot994-1 footprint information for reflow soldering of hvqfn24 package dimensions in mm ax ay bx by d slx sly spx tot spy tot spx spy gx gy hx hy 5.000 5.000 3.200 3.200 p 0.500 0.240 c 0.900 2.100 2.100 1.200 1.200 0.450 0.450 4.300 4.300 5.250 5.250 nspx nspy 22 sot994-1_fr occupied area ax bx slx gx gy hy hx aybysly p 0.025 0.025 d (0.105) spx tot spy tot nspx nspy spx spy solder land plus solder paste solder land solder paste deposit c generic footprint pattern refer to the package outline drawing for actual layout issue date 07-09-24 09-06-15
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 51 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 19. abbreviations 20. revision history table 40. abbreviations acronym description esd electrostatic discharge fet field-effect transistor gpio general purpose input/output i 2 c-bus inter-integrated circuit bus i/o input/output led light-emitting diode lsb least significant bit msb most significant bit pcb printed-circuit board por power-on reset smbus system management bus table 41. revision history document id release date data sheet status change notice supersedes pcal6416a v.3 20121224 product data sheet - pcal6416a v.2 modifications: ? added xlbga24 package option (pcal6416aex, sot1342-1) pcal6416a v.2 20121005 product data sheet - pcal6416a v.1 pcal6416a v.1 20120808 product data sheet - -
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 52 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander 21. legal information 21.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 21.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 21.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pcal6416a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 december 2012 53 of 54 nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 21.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 22. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pcal6416a low-voltage translating 16-bit i 2 c-bus/smbus i/o expander ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 24 december 2012 document identifier: pcal6416a please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 23. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 agile i/o features . . . . . . . . . . . . . . . . . . . . . . . 3 3 ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 voltage translation . . . . . . . . . . . . . . . . . . . . . . . 8 7 functional description . . . . . . . . . . . . . . . . . . . 9 7.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2 interface definition . . . . . . . . . . . . . . . . . . . . . . 9 7.3 pointer register and command byte . . . . . . . . . 9 7.4 register descriptions . . . . . . . . . . . . . . . . . . . 11 7.4.1 input port regist er pair (00h, 01h) . . . . . . . . . . 11 7.4.2 output port register pair (02h, 03h) . . . . . . . . 11 7.4.3 polarity inversion register pair (04h, 05h) . . . . 12 7.4.4 configuration register pa ir (06h, 07h) . . . . . . . 12 7.4.5 output drive streng th register pairs (40h, 41h, 42h, 43h) . . . . . . . . . . . . . . . . . . . . . . . . 13 7.4.6 input latch register pair (44h, 45h) . . . . . . . . . 13 7.4.7 pull-up/pull-down enable register pair (46h, 47h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4.8 pull-up/pull-down se lection register pair (48h, 49h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4.9 interrupt mask register pair (4ah, 4bh). . . . . . 15 7.4.10 interrupt status register pair (4ch, 4dh) . . . . . 16 7.4.11 output port configuration register (4fh) . . . . . 16 7.5 i/o port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.6 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 17 7.7 reset input (reset ) . . . . . . . . . . . . . . . . . . . 17 7.8 interrupt output (int ) . . . . . . . . . . . . . . . . . . . 18 8 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 write commands. . . . . . . . . . . . . . . . . . . . . . . 18 8.2 read commands . . . . . . . . . . . . . . . . . . . . . . 20 9 application design-in information . . . . . . . . . 24 9.1 minimizing i dd when the i/os are used to control leds . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2 output drive strength control . . . . . . . . . . . . . 25 9.3 power-on reset requirements . . . . . . . . . . . . . 26 9.4 device current cons umption with internal pull-up and pull-down resistors . . . . . . . . . . . . 28 9.5 i 2 c-bus error recovery techni ques . . . . . . . . . 28 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 29 11 recommended operating conditions. . . . . . . 30 12 thermal characteristics . . . . . . . . . . . . . . . . . 30 13 static characteristics . . . . . . . . . . . . . . . . . . . 31 13.1 typical characteristics . . . . . . . . . . . . . . . . . . 33 14 dynamic characteristics. . . . . . . . . . . . . . . . . 37 15 parameter measurement in formation . . . . . . 38 16 package outline. . . . . . . . . . . . . . . . . . . . . . . . 42 17 soldering of smd packages . . . . . . . . . . . . . . 46 17.1 introduction to soldering. . . . . . . . . . . . . . . . . 46 17.2 wave and reflow soldering. . . . . . . . . . . . . . . 46 17.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 46 17.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 47 18 soldering: pcb footprints . . . . . . . . . . . . . . . 49 19 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 51 20 revision history . . . . . . . . . . . . . . . . . . . . . . . 51 21 legal information . . . . . . . . . . . . . . . . . . . . . . 52 21.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 52 21.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 21.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 52 21.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 53 22 contact information . . . . . . . . . . . . . . . . . . . . 53 23 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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